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Hardware
while ((readSwitchReg(0x0405) & 1) != 0);
}
unsigned short readSwitchPhy(unsigned short _addr)
{
unsigned short rtn;
unsigned char vals[2];
// Note - Autopolling mode must be disabled
while ((readSwitchReg(0x0405) & 1) != 0);
writeSwitchReg(0x0400, (unsigned char)((_addr >> 8) & 0x000f));
writeSwitchReg(0x0401, (unsigned char)(_addr & 0x1f));
writeSwitchReg(0x0404, 0x02); // Read from Phy;
while ((readSwitchReg(0x0405) & 1) != 0);
vals[0] = readSwitchReg(0x0402);
vals[1] = readSwitchReg(0x0403);
rtn = (unsigned short) vals[0];
rtn += (((unsigned short) vals[1]) << 8);
return rtn;
}
int configVIAEthernetSwitch(void)
{
// Reset Switch (will PORESET dsps due to "strapping pins" shared)
*pdk_bd_regs.u711xpfc.cpld_gcr |= 0x0200;
pdk_waste_clks_10(100000);
*pdk_bd_regs.u711xpfc.cpld_gcr &= ~0x0200;
pdk_waste_clks_10(100000);
//
//
Confirm Communication with Switch
Check default MAC for Switch
if
if
if
if
if
if
(readSwitchReg(0x0619) != 0x00) {
(readSwitchReg(0x061a) != 0x40) {
(readSwitchReg(0x061b) != 0x63) {
(readSwitchReg(0x061c) != 0x80) {
(readSwitchReg(0x061d) != 0x00) {
(readSwitchReg(0x061e) != 0x00) {
return
return
return
return
return
return
1;
1;
1;
1;
1;
1;
}
}
}
}
}
}
// port configuration:
// 100Mbps, Full Duplex, Output and Input Enabled: 0x03
// Phy addresses are 0 and 1
writeSwitchReg(0x0418, 0x00);
writeSwitchReg(0x0419, 0x01);
writeSwitchReg(0x0420, 0x03);
if (readSwitchReg(0x0419) != 0x01) { return 1; } // Check write success
writeSwitchReg(0x0421, 0x03);
writeSwitchReg(0x0422, 0x03);
writeSwitchReg(0x0423, 0x03);
writeSwitchReg(0x0424, 0x03);
writeSwitchReg(0x0425, 0x03);
writeSwitchReg(0x0426, 0x03);
writeSwitchReg(0x0427, 0x03);
writeSwitchReg(0x0428, 0x03);
writeSwitchReg(0x0429, 0x03);
// PDK Phy Auto-Negotiation
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
14
Freescale Semiconductor
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